Author(s) Details:
Chaitanya Kommu
Department of EEC, GITAM University, Visakhapatnam, AP, India.
A Daisy Rani
Department of Instrument Technology, Andhra University, Visakhapatnam, AP, India.
This section is a part of the chapter: Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate
The rest of the paper is organized as follows: Session II discuss about overview of logic styles necessary for design, the design of three input XOR is explained in Session III and Session IV mentions the simulation setup and result discussion, finally in Session-V concludes the paper.
How to Cite
Kommu, C., & Rani, A. D. (2025). Presenting the Design of Low-Power High-Speed Two-Level Three input XOR Gate. Science and Technology: Developments and Applications Vol. 5, 1–14. https://doi.org/10.9734/bpi/stda/v5/2365